A peak current mode control (PCMC) is a control scheme for power converters enabling, in theory, certain desirable advantages like voltage feed forward, automatic cycle by cycle current limiting and other advantages known to persons skilled in the art. To implement this PCMC control scheme in practice, precisely controlled pulse width modulated (PWM) waveforms to drive control switches in power converters are essential. These power converters often employ a peak current reference without or with a slope compensation. The peak current reference is compared with a current sensed at the output of the power converter; the result of the comparison controlling the PWM waveform.
FIG. 1 depicts a conceptual block diagram of a digitally controlled PCMC based power converter system 100. A power converter 102 receives at its input an input voltage Vin from a source 104 and provides at its output a regulated voltage Vout to a load 106. To accomplish the Vout regulation, the Vout feedback is provided to block 108 comprising an analog-to-digital (ADC) converter, which digitizes the Vout feedback, which is then provided to a first input of a block 110 comprising a comparator and a voltage controller (not shown). A digital reference voltage Vref from a reference voltage source 112 is provided to a second input of the block 110. The digitized Vout—d feedback and the digital reference voltage Vref are compared by the comparator and the result of the comparison is provided to the voltage controller. Based on the comparison, the voltage controller generates voltage Vcomp, which is provided at the output of the voltage controller 110 and serves to derive a peak current reference signal Ipref.
It is well known by persons of ordinary skills in the art that PCMC based power converter systems suffer from stability issues and sub-harmonic oscillations for operation above 50% duty cycle theoretically. A duty cycle is the time that the PWM waveform spends in an active state. Consequently, the PCMC based power converter systems may implement a slope compensation. The slope compensation can be applied to the peak current Ipeak, decrementing the peak current Ipeak by a ramp thus arrive at a slope compensated peak current reference signal Ipref. Alternatively, the slope compensation may be achieved by keeping the peak current Ipeak constant and increment a feedback current Ifb by the ramp.
As depicted in FIG. 1, the feedback current Ifb is sensed at a node of converter 102 dependent on a topology of power converter, means of controlling the converter, and other design criteria known to persons skilled in the art. By means of example, the feedback current may be a current through the load 106; it could be a current through an inductor, transformer primary current, and other nodes known to persons skilled in the art.
For clarity of explanation of the different aspects the slope compensated peak current reference signal Ipref is used; however, the disclosed concepts are equally applicable to the case where the slope compensation ramp is added to the feedback current IfbIfb.
The generation of a slope compensated peak current reference signal Ipref is carried out by a block 114, comprising a digital-to-analog (DAC) converter, for converting the digital representation of the voltage Vout provided by the voltage controller 114 to an analog representation corresponding to a peak current Ipeak, and a ramp generator which generates a slope for compensation taking the value of the peak current Ipeak as initial value for the ramp generator.
The slope compensated peak current reference signal Ipref is provided to a first input of a block 116. The second input of the block 116 is provided with a feedback current Ifb corresponding to a sensed current in the power converter 102. The block 116 comprises a comparator (not shown), which compares the slope compensated peak current reference signal Ipref with the feedback current Ifb, and the result of the comparison affects various attributes of the PWM waveforms PWM(1)-PWM(n) generated by a PWM generator (not shown) of the block 116 and provided to the power converter 102.
Although as described above, blocks 108, 110, 114, 116, and 112 comprise a digital PCMC controller 101, persons skilled in the art would understand that not all the blocks need to be implemented in the digital PCMC controller 101. By means of an example, the slope compensation, i.e., the block 114 may or may not be implemented in the digital PCMC controller 101. Likewise, the comparator, described as a part of block 116, may be external to the digital PCMC controller 101. The digital PCMC controller 101 may optionally be interfaced with or reside inside a digital controller 117, e.g., a Microcontroller, Digital Signal Processor, and any other digital controller known to persons of ordinary skills in the art. The digital controller 117 may be utilized to program various attributes of the PWM waveforms and the slope for compensation; therefore, imparting more intelligence to the system and an ability to adaptively adjust to changing conditions for optimum digitally controlled PCMC based power converter system 100 performance.
The different implementation of the digital PCMC controller 101 may provide a different number of the PWM waveforms in accordance with a proposed use of a particular digital PCMC controller 101. However, it is understood by persons of ordinary skills in the art that not all the waveforms need to be generated and provided to the power converter. Thus, by means of an example a buck power converter may require a single PWM waveform, a synchronous buck power converter may require two PWM waveforms, an isolated phase shifted full bridge direct-current-to-direct-current (DC-DC) converter with synchronous rectification may require six waveforms, and the like.
As noted above, to achieve the above-mentioned theoretical advantages of the PCMC control scheme, generating precisely controlled timing of PWM waveforms to drive control switches in the power converters is essential. By means of an example, some power converters require that turning on and turning off two or more switches must be accurately adjusted. An example of such a power converter is the isolated phase shifted full bridge direct-current-to-direct-current (DC-DC) converter with synchronous rectification, where the synchronous rectifier switches need to be turned ON/OFF at precise, in some cases programmable, times relative to the time the feedback current reaches the peak current reference and relative to the PWM time period of the full bridge switches. By means of another example, some power converters require that two or more switches must be prevented to be turned on at the same time to prevent a current to simultaneously flow through the two or more switches, a fault known as “shoot-through.” An example of such a power converter 102 comprises a synchronous buck power converter. Because the two examples describe the same problem, generating precisely controlled PWM waveforms, which is accomplished by the same means, for the purposes of clarity of explanation of such a precise control, the synchronous buck power converter is used as an example without any loss of generality.
One technique for avoiding shoot-through provides timing between the turn-off of the first switch to the turn-on of the second switch and vice versa and is explained in reference to FIG. 2, which depicts a conceptual schematics of a synchronous buck power converter along with waveforms of interest 200. Although the term timing expresses the idea of generating precisely controlled timing of PWM waveforms to drive control switches in the power converters, because in relation to the shoot-through, the timing, i.e., the difference between the turn-off of the first switch to the turn-on of the second switch is called dead-time, the term is used in the example.
Referring to FIG. 2A, a power supply 204 provides an input voltage Vin to the synchronous buck power converter 202. As well known in the art, the circuitry of a synchronous buck converter comprises an (optional) input capacitor 202_1 to smooth a potential variation of the input voltage Vin, a pair of switches 202_2 and 202_3 that enable charge and discharge the inductor 202_4/capacitor 202_5 combination; thus regulating the output voltage Vout, which is provided to the load 206.
The switches 202_2 and 202_3 are driven by two PWM waveforms generated by a PWM waveform generator, e.g., the PWM waveform generator 116 of FIG. 1 (not shown in FIG. 2A). Such a PWM waveform generator must generate the two PWM waveforms such that the switches 202_2 and 202_3 are prevented to be turned on at the same time.
FIG. 2B depicts an amplitude as a function of time of selected waveforms facilitating understanding of the timing technique.
Referring to FIG. 2B, at time t0, which marks an end of a previous PWM period and a start of a new PWM period, the slope compensated peak current reference signal Ipref 224, is reset to a peak current value Ipeak and a ramp is decremented from the a peak current value Ipeak for the slope compensation. At the same time, the first PWM waveform 218 is reset from an amplitude A1—2 to an amplitude A1—1; thus, causing switch 202_3 of FIG. 2A, to open. The feedback current Ifb 222 keeps decreasing.
After a first dead-time DT1, i.e., at time t1, the second PWM waveform 220 is set from an amplitude A2—1 to an amplitude A2—2; thus, causing switch 202_2 of FIG. 2A, to close; thus causing the feedback current Ifb 222 to start increasing until reaching the limit set by the slope compensated peak current reference signal Ipref 224 at time t2, when the second PWM waveform 220 is reset from the amplitude A2—2 to an amplitude A2—1; the reset causing switch 202_2 of FIG. 2A, to open, thus causing the feedback current Ifb 222 to start decreasing.
After a second dead-time DT2, i.e., at time t3, the first PWM waveform 218 is set from the amplitude A1—1 to the amplitude A1—2; thus, causing switch 202_3 of FIG. 2A, to close; thus keeping the feedback current Ifb 222 decreasing.
At time t4 the PWM period ends, the first PWM waveform 218 is reset from an amplitude A1—2 to an amplitude A1—1, the slope compensated peak current reference signal Ipref 224, is reset to a peak current value Ipeak and the PWM period is repeated.
Based on the foregoing description, the start of dead-time DT1 is initiated by an event generated at the instant the feedback current Ifb reaches the peak reference signal Ipref. This event is based on factors external to the IC for PCMC controller. Although the PCMC controller itself could take an action based on the detection, the timing is generated by an external support circuit. Accordingly, achieving variable delay could be achieved by implementing a plurality of such external support circuit. Such a solution is in practice limited to about five external support circuits, due to power, real-state area, power requirements and other practical considerations.
Consequently, there is a need in the art to provide a solution to at least some of the above-disclosed problems.